Liquid crystal display panel and manufacturing method thereof

ABSTRACT

A liquid crystal display (LCD) panel and manufacturing method thereof capable of ensuring an aperture ratio while reducing the number of data lines by a change of an arrangement structure of subpixels includes a plurality of subpixels constituting a display region, a plurality of thin film transistors (TFTs) connected respectively to the plurality of subpixels, a plurality of gate lines connected to the TFTs and formed along long sides of the subpixels, a plurality of data lines connected to the TFTs and formed along short sides of the subpixels, a plurality of storage lines formed to pass through the subpixels along the short sides of the subpixels, a first common storage line connected commonly to one end of each of the plurality of storage lines, and a second common storage line connected commonly to an opposite end of each of the plurality of storage lines.

This application is a continuation application of U.S. application Ser.No. 11/487,075, filed Jul. 14, 2006, which claims priority to KoreanPatent Application No. 2006-0004233, filed on Jan. 16, 2006, and all thebenefits accruing therefrom under 35 U.S.C. §119, and the contents ofwhich in its entirety are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a liquid crystal display (“LCD”)apparatus, and more particularly, to an LCD panel and manufacturingmethod thereof capable of reducing the number of data lines andminimizing a reduction in an aperture ratio caused by storage lines.

2. Description of the Related Art

An LCD apparatus displays an image by using electro-optical propertiesof liquid crystals disposed between electrodes of an LCD panel. The LCDapparatus includes the LCD panel for displaying an image through a pixelmatrix and a driving circuit for driving the LCD panel. The LCDapparatus further includes a backlight unit for supplying light from therear of the LCD panel because the LCD panel is a non-emitting device.The LCD apparatus is widely used in display devices ranging fromsmall-sized display devices such as mobile communication terminals,notebook computers and LCD TVs to large-sized display devices.

The LCD panel in which pixels each consisting of red, green and bluesubpixels are arrayed in a matrix form displays an image by adjustingthe transmittance of light irradiated from the backlight unit while therespective subpixels vary the arrangement of the liquid crystalsaccording to a data signal. The subpixels drive the liquid crystals bycharging a difference voltage between a data signal supplied to a pixelelectrode through a thin film transistor (“TFT”) of a switching elementand a common voltage supplied to a common electrode. A plurality of gateintegrated circuits (“ICs”) for driving gate lines connected to TFTs anda plurality of data ICs for driving data lines are connected to the LCDpanel. The data ICs have a more complicated circuit structure than thatof the gate ICs because the data ICs should convert digital video datainto an analog data signal.

In order to lower the cost, the LCD panel has been developed to reducethe number of data lines while maintaining resolution. To reduce thenumber of data lines, a method of changing an arrangement structure ofthe subpixels is used. In this case, an aperture ratio should be ensuredso as not to degrade luminance and picture quality.

BRIEF SUMMARY OF THE INVENTION

The present invention thus provides an LCD panel and manufacturingmethod thereof capable of ensuring an aperture ratio while reducing thenumber of data lines by changing an arrangement structure of thesubpixels.

In accordance with one exemplary embodiment of the present invention,there is provided an LCD panel including a plurality of subpixelsconstituting a display region, a plurality of thin film transistors(TFTs) connected respectively to the plurality of subpixels, a pluralityof gate lines connected to the TFTs and formed along long sides of thesubpixels, a plurality of data lines connected to the TFTs and formedalong short sides of the subpixels, a plurality of storage lines formedto pass through the subpixels along the short sides of the subpixels, afirst common storage line connected commonly to one end of each of theplurality of storage lines, and a second common storage line connectedcommonly to the other end of each of the plurality of storage lines.

The plurality of subpixels includes red, green and blue subpixels, andthe red, green and blue subpixels are alternately repeatedly arrayedalong the data lines.

The first and second common storage lines are formed of a first metallayer which is the same as the gate lines, and the storage lines areformed of a second metal layer which is the same as the data lines.

The LCD panel further includes a plurality of first contact electrodesconnecting the first common storage line to the plurality of storagelines, and a plurality of second contact electrodes connecting thesecond common storage line to the plurality of storage lines.

Each of the first and second contact electrodes is formed of a thirdconductive layer connecting the common storage lines to the storagelines through contact holes exposing the common storage lines and thestorage lines.

The first common storage line is connected to an upper part of theplurality of storage lines via an upper non-display region out of anon-display region encompassing the display region, and the secondcommon storage line is connected to a lower part of the plurality ofstorage lines via a lower non-display region. The second common storageline extends to the upper non-display region along right and leftnon-display regions in the lower non-display region.

The LCD panel further includes a first common pad connected to opposingends of the first common storage line, and a second common pad connectedto opposing ends of the second common storage line.

Alternatively, the LCD panel further includes a common pad connectedcommonly to the corresponding opposing ends of each of the first andsecond common storage lines.

The LCD panel further includes gate drivers installed in the right andleft non-display regions, for separately driving the plurality of gatelines. The second common storage line passes by an outbound side of thegate drivers.

In accordance with another exemplary embodiment of the presentinvention, there is provided a method of manufacturing an LCD panel,including forming a gate line, a data line and a TFT connected to thegate and data lines on a substrate, forming a subpixel connected to theTFT in each subpixel region defined by a crossing structure of the gateand data lines, the subpixel region having a long side in parallel withthe gate line and a short side in parallel with the data line, forming astorage line passing through the pixel electrode in a direction of theshort line of the subpixel region, and forming first and second commonstorage lines connected respectively to one end and an opposite otherend of the storage line.

The first and second common storage lines are formed of a first metallayer which is the same as the gate line, and the storage line is formedof a second metal layer which is the same as the data line.

The method of manufacturing an LCD panel further includes forming afirst contact electrode for connecting the first common storage line tothe storage line and a second contact electrode for connecting thesecond common storage line to the storage line.

The forming the first and second contact electrodes includes formingcontact holes for exposing the common storage lines and the storageline, and forming the first and second contact electrodes of a thirdconductive layer for connecting the common storage lines to the storageline through the contact holes.

The method of manufacturing an LCD panel further includes forming afirst common pad connected to opposing ends of the first common storageline and a second common pad connected to opposing ends of the secondcommon storage line.

Alternatively, the method of manufacturing an LCD panel further includesforming a common pad connected commonly to opposing ends of the firstand second common storage lines.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present inventionwill become more apparent from the following detailed description whentaken in conjunction with the accompanying drawings in which:

FIG. 1 is a plan view illustrating part of an exemplary embodiment of anLCD apparatus according to the present invention;

FIG. 2 is a diagram illustrating an exemplary embodiment of a TFTsubstrate of an LCD panel according to the present invention;

FIG. 3 is an enlarged cross-sectional view of a storage capacitor formedin one subpixel region shown in FIG. 2;

FIG. 4 is an enlarged cross-sectional view of a connector of a storageline shown in FIG. 2; and

FIG. 5 is a diagram illustrating another exemplary embodiment of a TFTsubstrate of an LCD panel according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The invention will now be described more fully hereinafter withreference to the accompanying drawings, in which embodiments of theinvention are shown. This invention may, however, be embodied in manydifferent forms and should not be construed as limited to theembodiments set forth herein. Rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the scope of the invention to those skilled in the art. Likereference numerals refer to like elements throughout.

It will be understood that when an element is referred to as being “on”another element, it can be directly on the other element or interveningelements may be present therebetween. In contrast, when an element isreferred to as being “directly on” another element, there are nointervening elements present. As used herein, the term “and/or”includesany and all combinations of one or more of the associated listed items.

It will be understood that, although the terms first, second, third etc.may be used herein to describe various elements, components, regions,layers and/or sections, these elements, components, regions, layersand/or sections should not be limited by these terms. These terms areonly used to distinguish one element, component, region, layer orsection from another element, component, region, layer or section. Thus,a first element, component, region, layer or section discussed belowcould be termed a second element, component, region, layer or sectionwithout departing from the teachings of the present invention.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” or “includes” and/or “including” when used in thisspecification, specify the presence of stated features, regions,integers, steps, operations, elements, and/or components, but do notpreclude the presence or addition of one or more other features,regions, integers, steps, operations, elements, components, and/orgroups thereof Spatially relative terms, such as “beneath”, “below”,“lower”, “above”, “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. It will beunderstood that the spatially relative terms are intended to encompassdifferent orientations of the device in use or operation in addition tothe orientation depicted in the figures. For example, if the device inthe figures is turned over, elements described as “below” or “beneath”other elements or features would then be oriented “above” the otherelements or features. Thus, the exemplary term “below” can encompassboth an orientation of above and below. The device may be otherwiseoriented (rotated 90 degrees or at other orientations) and the spatiallyrelative descriptors used herein interpreted accordingly.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this invention belongs. It will befurther understood that terms, such as those defined in commonly useddictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art and thepresent disclosure, and will not be interpreted in an idealized oroverly formal sense unless expressly so defined herein.

The exemplary embodiments of the present invention will now be describedwith reference to FIGS. 1 to 5.

FIG. 1 is a plan view schematically illustrating part of an exemplaryembodiment of an LCD apparatus according to the present invention.

The LCD apparatus illustrated in FIG. 1 includes an image display unit16, an LCD panel 10 in which first and second gate drivers 12 and 14,respectively, for driving gate lines of the image display unit 16 areformed, a circuit film 6 mounting a data IC 8 for driving data lines ofthe image display unit 16 thereon and being connected between a printedcircuit board (“PCB”) 2 and the LCD panel 10, and a timing controller 4mounted on the PCB 2.

The image display unit 16 of the LCD panel 10 displays an image by aplurality of pixels arrayed in a matrix form, each pixel consisting ofred (R), green (G) and blue (B) subpixels. A TFT substrate where TFTsare formed with respect to the R, G and B subpixels and a color filtersubstrate where color filters are formed are sealed together with liquidcrystals therebetween, thereby forming the image display unit 16. Gatelines, data lines and pixel electrodes connected to the TFTs are furtherformed on the TFT substrate. A common electrode for driving the liquidcrystals together with the pixel electrodes is formed on the TFTsubstrate or the color filter substrate. The R, G and B subpixels arealternately repeatedly arranged in the vertical direction and thesubpixels of the same color are horizontally arranged in a stripe shape.In other words, the image display unit 16 has a structure in which an Rhorizontal line consisting of a plurality of R subpixels, a G horizontalline consisting of a plurality of G subpixels, and a B horizontal lineconsisting of a plurality of B subpixels are alternately repeatedlyarrayed in the vertical direction. Each of the R, G and B subpixels hasa rectangle shape of which longer sides of each rectangle are orientedin a horizontal direction and the other sides are oriented in a verticaldirection as illustrated in FIG. 1. By the vertical arrangement of theR, G and B subpixels on the image display unit 16, the inventive LCDpanel reduces the number of data lines to one third compared to theprior art LCD panel in which the R, G and B subpixels are arrayed in thehorizontal direction. As a result, the number of data ICs 8 for drivingthe data lines is reduced. The magnitude of the gate drivers 12 and 14increases because the number of gate lines increases as the number ofdata lines decreases due to the vertical arrangement of the R, G and Bsubpixels. However, since the circuit structure of the gate drivers 12and 14 is simpler than that of the data ICs 8, the manufacturing cost isless. Especially, since the gate drivers 12 and 14 are installed withinthe LCD panel 10 using an amorphous silicon thin film, the manufacturingcost can be even less.

The first and second gate drivers 12 and 14 are located at opposingsides of the image display unit 16 and separately drive the gate lines.For example, the first gate driver 12 drives the odd-numbered gate linesand the second gate driver 14 drives the even-numbered gate lines. Thefirst and second gate drivers 12 and 14 are comprised of shift registersincluding a plurality of TFTs. The first and second gate drivers 12 and14 are each formed on the TFT substrate of the LCD panel 10, togetherwith TFTs and a plurality of signal lines of the image display unit 16,and installed in a non-display region.

Each of a plurality of data ICs 8 for separately driving the data linesof the image display unit 16 is mounted on the circuit film 6. Thecircuit film 6 is attached to the LCD panel 10 and the PCB 2 through ananisotropic conductive film (“ACF”). A tape carrier package (“TCP”) or achip-on-film (“COF”) is used as the circuit film 6 on which the data IC8 is mounted. It is possible to directly mount the data IC 8 on the TFTsubstrate of the LCD panel 10 by using chip-on-glass (“COG”) technologywithout using the circuit film 6.

The timing controller 4 mounted on the PCB 2 controls the data ICs 8 andthe first and second gate drivers 12 and 14. A plurality of data signalsand data control signals from the timing controller 4 are supplied toeach data IC 8 via the PCB 2 and the circuit film 6, and a plurality ofgate control signals from the timing controller 4 is supplied to thefirst and second gate drivers 12 and 14 via the PCB 2, the circuit film6, and the TFT substrate of the LCD panel 10.

The first and second gate drivers 12 and 14 sequentially drive the gatelines of the image display unit 16 by using the gate control signalsfrom the timing controller 4 and gate ON and OFF voltages from a powersource (not shown). The data ICs 8 convert digital data signals from thetiming controller 4 into analog data signals by using gamma voltagesfrom a gamma voltage part (not shown) and supply the analog data signalsto the data lines in synchronization with each horizontal period duringwhich the gate lines of the image display unit 16 are driven.

FIG. 2 is a plan view schematically illustrating the TFT substrate ofthe LCD panel shown in FIG. 1.

A TFT substrate 11 shown in FIG. 2 is divided into a display regioncorresponding to the image display unit 16 of the LCD panel 10 shown inFIG. 1 and a non-display region encompassing the display region. Gatelines GL1 to GLm and data lines DL1 to DLn+1 are formed in a crossingstructure in the display region of the TFT substrate 11, and a pixelelectrode 46 and a TFT are formed in each subpixel region defined by thecrossing structure. The TFT supplies a data signal from the data line tothe pixel electrode 46 in response to a gate signal from the gate line.The pixel electrode 46 has a longer side in the horizontal directionthan the other side in the vertical direction as a result of thevertical direction arrangement of the R, G and B subpixels. The pixelelectrode 46 determines the size and shape of a subpixel together with acolor filter of the color filter substrate.

In order to prevent liquid crystals from being degraded, the polarity ofthe data signal supplied to the data lines DL1 to DLn+1 should beinverted at a predetermined period. A dot inversion scheme providesexcellent picture quality by driving each subpixel to have oppositepolarity to horizontally and vertically adjacent subpixels. For the dotinversion scheme, however, the data signal supplied to the data linesDL1 to DLn+1 should be inverted on a subpixel basis. Then the swingwidth and driving frequency of the data signal increase, and thus thedot inversion scheme has a shortcoming in terms of power consumption. Tosolve such a problem, the connecting directions of the TFTs connected tothe data lines DL1 to DLn+1 are constructed to be alternately changedalong the vertical direction. For example, the TFTs of odd-numberedhorizontal lines connected to the odd-numbered gate lines GL1, GL3, . .. , GLm are connected to the pixel electrodes 46 on the right of thedata lines DL1 to DLn. The TFTs of even-numbered horizontal linesconnected to the even-numbered gate lines GL2, GL4, . . . , GLm−1 areconnected to the pixel electrodes 46 on the left of the data lines DL2to DLn+1. Accordingly, the polarity of the data signal supplied to eachof the data lines DL1 to DLn+1 is opposite to that of the data signalsupplied to the adjacent data lines. Even if the polarity of the datasignal is inverted only on a frame basis, the pixel electrode 46 chargesthe data signal of the opposite polarity to the horizontally andvertically adjacent pixel electrodes 46 to be driven by the dotinversion scheme.

Storage lines SL1 to SLn for forming storage capacitors of the subpixelsare formed in parallel with the data lines DL1 to DLn+1 in the displayregion of the TFT substrate 11. The storage lines SL1 to SLn cross thegate lines GL1 to GLm and pass through the pixel electrodes 46 in thevertical (short side) direction. Since an overlapped area of the storageline with the pixel electrode 46 is smaller than when the storage linesSL1 to SLn are formed in parallel with the gate lines GL1 to GLm andoverlapping the horizontal (long side) direction of the pixel electrode46, an aperture ratio can be improved. The storage lines SL1 to SLn areformed of a source/drain metal by the same mask process as the datalines DL1 to DLn+1. In other words, a storage line SL is formed of asource/drain metal on a gate insulating layer 42 as illustrated in FIG.3, and the gate insulating layer 42 is formed on an insulating substrate40. A storage capacitor Cst of each subpixel is formed such that thepixel electrode 46 overlaps the storage line SL with a passivation layer44 therebetween.

The first and second gate drivers 12 and 14 for separately driving thegate lines GL1 to GLm are respectively formed in the left and rightnon-display regions, respectively, of the TFT substrate 11 with thedisplay region therebetween. For instance, the first gate driver 12 inthe left non-display region drives the odd-numbered gate lines GL1, GL3,. . . , GLm, and the second gate driver 14 in the right non-displayregion drives the even-numbered gate lines GL2, GL4, . . . , GLm−1. Thefirst and second gate drivers 12 and 14 are comprised of a plurality ofTFTs and they are formed together with TFTs of the display region.

First and second common storage lines 22 and 24 are connected commonlyto the storage lines SL1 to SLn, and a plurality of first and secondcontact electrodes 30 and 32, respectively, for connecting the first andsecond common storage lines 22 and 24 to the storage lines SL1 to SLn.The first and second common storage lines 22 and 24 are formed in thenon-display region encompassing the image display unit of the TFTsubstrate 11. The first and second common storage lines 22 and 24 aresimultaneously connected to the upper and lower parts of the storagelines SL1 to SLn, respectively. If any one of the first and secondcommon storage lines 22 and 24 is shorted, a common voltage can besupplied through the other common storage line. That is, the first andsecond common storage lines 22 and 24 serve as mutual redundancy.

The first common storage line 22 is formed in the upper non-displayregion of the TFT substrate 11 and is connected commonly to the upperpart of the storage lines SL1 to SLn through the first contactelectrodes 30. The first common storage line 22 extends to opposingsides of the upper non-display region and is connected to output pads ofthe first and last circuit films 6 shown in FIG. 1 through two firstcommon pads 21. The first common storage line 22 receives a commonvoltage from a power source (not shown) mounted on the PCB 2 shown inFIG. 1 via the PCB 2 and the circuit films 6, and commonly supplies thecommon voltage to the storage lines SL1 to SLn.

The second common storage line 24 is formed in the lower non-displayregion of the TFT substrate 11 and is connected commonly to the lowerpart of the storage lines SL1 to SLn through the second contactelectrodes 30. The second common storage line 24 extends to opposingsides of the lower non-display region and includes a bent portions ateach opposing end. The second common storage line 24 further extendsfrom the bent portions to the upper side along the right and leftnon-display regions and is connected to output pads of the first andlast circuit films 6 shown in FIG. 1 through two second common pads 23.At this time, the second common storage line 24 extends to the upperside via passing by an outer side or outbound side of the first andsecond gate drivers 12 and 14 in the left and right non-display regions,respectively. Therefore, the second common storage line 24 receives thecommon voltage from the power source (not shown) mounted on the PCB 2shown in FIG. 1 via the PCB 2 and the circuit films 6, and commonlysupplies the common voltage to the storage lines SL1 to SLn.

The first and second common storage lines 22 and d24 are formed of agate metal by the same mask process as the gate lines of the displayregion. The first and second contact electrodes 30 and 32 and the pixelelectrodes 46 of the display region are formed of a transparentconductive layer by the same mask process.

As illustrated in FIG. 4 for example, the first contact electrode 30 isconnected to the first common storage line 22 and the storage line SLthrough first and second contact holes 34 and 36. The first commonstorage line 22 is formed of a gate metal on the insulating substrate 40and the gate insulating layer 42 is formed on the first common storageline 22. The storage line SL is formed of a source/drain metal on thegate insulating layer 42 and the passivation layer 44 is formed on thestorage line SL. The first contact hole 34 penetrates the passivationlayer 44 and the gate insulating layer 42 to expose a part of the firstcommon storage line 22, and the second contact hole 36 penetrates thepassivation layer 44 to expose a part of the storage line SL. The firstcontact electrode 30 formed on the passivation layer 44 connects thefirst common storage line 22 to the storage line SL via the first andsecond contact holes 34 and 36. The second contact electrode 32 connectsthe second common storage line 24 to the storage line SL by the samestructure as the first contact electrode 30 shown in FIG. 4.

The first common pad 21 connected to the first common storage line 22and the second common pad 23 connected to the second common storage line24 are separately formed as shown in FIG. 2 and connected to the outputpads provided in the circuit film 6 shown in FIG. 1. Alternatively, thefirst and second common storage lines 22 and 24 are connected to theoutput pads provided in the circuit film 6 shown in FIG. 1 through anidentical common pad 20 as shown in FIG. 5. A plurality of gate drivingsignal input pads (not shown) are positioned between the first andsecond common pads 21 and 23 that are connected to one circuit film 6and separated from each other. The plurality of gate driving signalinput pads are connected to a plurality of gate driving signal supplylines connected to the gate drivers 12 and 14 and supplies to the gatedrivers 12 and 14 a plurality of gate driving signals received via thecircuit film 6 from the power source and timing controller 4 on the PCB2 shown in FIG. 1.

As described above, the LCD panel according to the present inventionreduces the number of data lines by arranging the R, G and B subpixelsin the vertical direction. The long sides of the R, G and B subpixelsare formed in parallel with the gate lines and the short sides thereofare formed in parallel with the data lines. The storage lines are formedin parallel with the data lines to pass through the subpixels in thedirection of the short sides. Therefore, a reduction of an apertureratio caused by the storage lines is minimized and the aperture ratiocan be ensured compared to the storage lines passing through thesubpixels in the direction of the long sides.

As apparent from the foregoing description, the manufacturing method ofan LCD panel according to the present invention array the R, G and Bsubpixels in the vertical direction to reduce the number of the datalines. The storage lines are formed in parallel with the data lines andpass through the subpixels in the direction of short sides. Therefore, areduction of an aperture ratio caused by the storage lines is minimizedand the aperture ratio can be ensured.

Moreover, the first and second common storage lines are simultaneouslyconnected to the upper and lower parts of a plurality of storage lines.Therefore, even if any one of the common storage lines is shorted, theother common storage line can supply the common voltage to the storagelines.

While the invention has been shown and described with reference to acertain exemplary embodiments thereof, it will be understood by thoseskilled in the art that various changes in form and details may be madetherein without departing from the spirit and scope of the invention asdefined by the appended claims.

1. A liquid crystal display (LCD) panel, comprising: a plurality ofsubpixels constituting a display region; a plurality of thin filmtransistors (TFTs) connected respectively to the plurality of subpixels;a plurality of gate lines connected to the TFTs and formed along longsides of the subpixels; a plurality of data lines connected to the TFTsand formed along short sides of the subpixels; a plurality of storagelines formed to pass through the subpixels along the short sides of thesubpixels; a first common storage line connected commonly to one end ofeach of the plurality of storage lines.
 2. The LCD panel as claimed inclaim 1, wherein the plurality of subpixels includes red, green and bluesubpixels and the red, green and blue subpixels are alternatelyrepeatedly arrayed along the data lines.
 3. The LCD panel as claimed inclaim 2, wherein the first common storage line is formed of a firstmetal layer which is the same as the gate lines, and the storage linesare formed of a second metal layer which is the same as the data lines.4. The LCD panel as claimed in claim 3, further comprising: a pluralityof first contact electrodes for connecting the first common storage lineto the plurality of storage lines.
 5. The LCD panel as claimed in claim4, wherein each of the first contact electrodes is formed of a thirdconductive layer for connecting the common storage lines to the storagelines through contact holes exposing the common storage lines and thestorage lines.
 6. The LCD panel as claimed in claim 2, furthercomprising: a plurality of first contact electrodes for connecting thefirst common storage line to the plurality of storage lines.
 7. The LCDpanel as claimed in claim 6, wherein each of the first contactelectrodes is formed of a third conductive layer for connecting thecommon storage lines to the storage lines through contact holes exposingthe common storage lines and the storage lines.
 8. The LCD panel asclaimed in claim 1, further comprising gate drivers disposed at anon-display region.
 9. The LCD panel as claimed in claim 8, wherein thefirst common storage line is formed of a first metal layer which is thesame as the gate lines, and the storage lines are formed of a secondmetal layer which is the same as the data lines.
 10. The LCD panel asclaimed in claim 9, further comprising: a plurality of first contactelectrodes for connecting the first common storage line to the pluralityof storage lines.
 11. The LCD panel as claimed in claim 10, wherein eachof the first contact electrodes is formed of a third conductive layerfor connecting the common storage lines to the storage lines throughcontact holes exposing the common storage lines and the storage lines.12. The LCD panel as claimed in claim 8, further comprising: a pluralityof first contact electrodes for connecting the first common storage lineto the plurality of storage lines.
 13. The LCD panel as claimed in claim12, wherein each of the first contact electrodes is formed of a thirdconductive layer for connecting the common storage lines to the storagelines through contact holes exposing the common storage lines and thestorage lines.
 14. A liquid crystal display (LCD) panel, comprising: aplurality of subpixels constituting a display region; a plurality ofthin film transistors (TFTs) connected respectively to the plurality ofsubpixels; a plurality of gate lines connected to the TFTs and formedalong long sides of the subpixels; a plurality of data lines connectedto the TFTs and formed along short sides of the subpixels; a pluralityof storage lines formed to pass through the subpixels along the shortsides of the subpixels; and gate drivers disposed at a non-displayregion.
 15. The LCD panel as claimed in claim 14, further comprising afirst common storage line connected commonly to one end of each of theplurality of storage lines, wherein the first common storage line isparallel with the gate lines.
 16. The LCD panel as claimed in claim 15,wherein the gate drivers are disposed at a right and left non-displayregion.
 17. The LCD panel as claimed in claim 16, wherein the firstcommon storage line is connected to a circuit film.
 18. The LCD panel asclaimed in claim 15, wherein the first common storage line is connectedto a circuit film.
 19. The LCD panel as claimed in claim 14, wherein thegate drivers are disposed at a right and left non-display region. 20.The LCD panel as claimed in claim 19, wherein the first common storageline is connected to a circuit film.
 21. The LCD panel as claimed inclaim 14, wherein the first common storage line is connected to acircuit film.
 22. A liquid crystal display (LCD) panel, comprising: aplurality of subpixels constituting a display region; a plurality ofthin film transistors (TFTs) connected respectively to the plurality ofsubpixels; a plurality of gate lines connected to the TFTs and formedalong long sides of the subpixels; a plurality of data lines connectedto the TFTs and formed along short sides of the subpixels; a pluralityof storage lines formed to pass through the subpixels along the shortsides of the subpixels; and gate drivers disposed at a non-displayregion; wherein the plurality of subpixels includes red, green and bluesubpixels and the red, green and blue subpixels are alternatelyrepeatedly arrayed along the data lines.
 23. The LCD panel as claimed inclaim 22, further comprising a first common storage line connectedcommonly to one end of each of the plurality of storage lines, whereinthe first common storage line is parallel with the gate lines.
 24. TheLCD panel as claimed in claim 23, wherein the gate drivers are disposedat a right and left non-display region.
 25. The LCD panel as claimed inclaim 24, wherein the first common storage line is connected to acircuit film.
 26. The LCD panel as claimed in claim 23, wherein thefirst common storage line is connected to a circuit film.
 27. The LCDpanel as claimed in claim 22, wherein the gate drivers are disposed at aright and left non-display region.
 28. The LCD panel as claimed in claim27, wherein the first common storage line is connected to a circuitfilm.
 29. The LCD panel as claimed in claim 22, wherein the first commonstorage line is connected to a circuit film.